Apparatus and method for reducing photo leakage current for tft lcd

ABSTRACT

In one aspect of the invention, the method of forming a TFT array panel includes forming a patterned first conductive layer on a substrate, forming a gate insulating layer on the patterned first conductive layer and the substrate, forming a patterned semiconductor layer on the gate insulating layer, forming a patterned second conductive layer, forming a patterned passivation layer on the patterned second conductive layer and the substrate, and forming a patterned transparent conductive layer on the patterned passivation layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of, and claims benefit ofU.S. patent application Ser. No. 11/873,674, filed Oct. 17, 2007,entitled “APPARATUS AND METHOD FOR REDUCING PHOTO LEAKAGE CURRENT FORTFT LCD”, by Ching-Chieh Shih, et al., which status is allowed, thedisclosure of which is hereby incorporated herein in its entirety byreference.

FIELD OF THE INVENTION

The present invention relates generally to an apparatus and a method forreducing photo leakage current for TFT liquid crystal display.

BACKGROUND OF THE INVENTION

Electronic matrix arrays are usually used in devices such as liquidcrystal displays (LCD). Such devices are typically arranged in row andcolumn address lines. These lines are horizontally and vertically spacedapart and cross at an angle to one another and a plurality of crossoverpoints are formed. Each crossover point is associated with acorresponding display element to be selectively addressed. The displayelement may be a pixel of an imager array, or alternatively a pixel ofan LCD. A switching or isolation device such as a thin film transistor(TFT) is associated with each display element allowing individual pixelsin the LCD to be selectively addressed.

Structurally, these TFTs typically include a source electrode, a drainelectrode, and a gate electrode, with a thin film of semiconductormaterial (e.g. amorphous silicon or a-Si) disposed between the sourceand drain electrodes. The gate electrode in proximity to thesemiconductor but electrically insulated by a gate insulator. Currentflow through the TFT between the source and drain electrodes iscontrolled by the application of voltage to the gate electrode. Theapplication of a positive voltage (e.g. +10 volts) to the gate of theTFT forms a conducting channel and allows current to flow between thesource and drain electrodes of the TFT.

The drain electrode of a TFT is usually in electrical communication witha pixel electrode. Thus, the source electrode of the TFT is usually inelectrical communication with an image signal input. In an LCDapplications for example, when a voltage (e.g. +10 volts) is applied tothe gate and at the same time a video voltage (e.g. +5 volts) is appliedthrough the image signal input to the source of a TFT, a conductivechannel is formed in the semiconductor layer and current flows throughfrom the drain electrode to the source electrode. This current chargesthe corresponding pixel electrode of the LCD causing the pixel to be inan “on-state.” In LCD applications, the drain typically reaches avoltage similar to that is supplied to the source through the imagesignal input in the on-state. The amplitude of the voltage applied tothe source through the image signal input thus determines how muchvoltage will be applied across the liquid crystal material in a givenpixel and thus controls gray scale levels of the display. When voltageis no longer applied to the gate, the pixel stops charging but remainson until the next frame.

Conventionally, the TFT is made of an “island out” structure 200 asillustrated in FIGS. 5A, 5B and 5C. This structure is directlyresponsible for the generation of the undesirable leak photo currentthat reduces the performance of the TFT LCDs. FIG. 5A shows a top viewand FIG. 5B shows a sectional view of the “island out” TFT structure200. As illustrated in FIG. 5B, a gate electrode metal portion 210 isformed on a substrate 205. A gate insulation layer 212 is formed on thegate electrode metal portion 210. Additionally, a layer of intrinsicsemiconductor 214 and a layer of doped semiconductor 216 are formed onthe gate insulation layer 212. Moreover, a conductive layer 218 forsource electrode 202 and drain electrode 204 covers the layer ofintrinsic semiconductor 214 and the layer of doped semiconductor 216.FIG. 5C shows a detailed sectional view of an “island out” TFT structure200 along the B-B′ plane as shown in FIG. 5A. A passivation layer 220and a transparent conductive layer (i.e. indium, tin oxide, or ITO) 222are formed on top of the TFT structure surface shown in FIG. 5B.

As it is known to those skilled in the art, one of the characteristicsof the semiconductor amorphous silicon using the “island out” TFTstructure is that the amorphous silicon produces “photo current” (i.e. aleakage current from the source to the drain through the semiconductorlayer when the pixel is in an on-state) under normal or strong lighting.Accordingly, a TFT's photo leakage current is a critical elementdetermining the overall image quality of LCDs. It is well known thathigh TFT leakage current degrades performance of an LCD display. Theadverse effects include inconsistent/non-uniform gray scales, crosstalk,shading, flicker, and/or image sticking This leakage current is anundesirable and unintentional characteristics associated withconventional TFT made of semiconductor materials such as amorphoussilicon or a-Si and using the “island out” TFT structure.

Various attempts have been made to minimize TFT leakage current. Forexample, for crystalline-silicon and polycrystalline silicon TFTs,lightly doped drain or drain offset structures have been experimented.However, that approach requires additional process steps (i.e. photo,ion implantation, etc.). An alternative is to use an “island in” TFTstructure 300 as illustrated in FIGS. 6A and 6B. FIG. 6A shows a topview and FIG. 6B shows a sectional view of the “island in” TFT structure300. A gate electrode metal portion 310 is formed on a substrate 305.Additionally, a gate insulation layer 312 is formed on the gateelectrode metal portion 310. A layer of intrinsic semiconductor 314 anda layer of doped semiconductor 316 are formed on the gate insulationlayer 312. As shown in FIG. 6B, the layer of intrinsic semiconductor 314and the layer of doped semiconductor 316 are rather narrow in comparisonwith the corresponding counterparts of the “island out” TFT structureshown in FIG. 5B. A conductive layer 318 for source electrode 302 anddrain electrode 304 covers the layer of intrinsic semiconductor 314 andthe layer of doped semiconductor 316. Since the size of the intrinsicsemiconductor (amorphous silicon) is reduced, the amorphous silicon'sexposure to the light is greatly reduced. Therefore, the photo leakagecurrent is reduced as well.

Although the “island in” TFT structure reduces the photo leakagecurrent, it requires additional mask, photolithographic and etchingprocesses, which makes it undesirable for mass production. In order toconsolidate the processing steps in mass production, normally intrinsicamorphous silicon and the source and drain electrode metal are depositedon the gate insulation layer at the same time. This process dictatesthat a TFT made by this process must use the “island out” TFT structure.

Therefore, a heretofore unaddressed need exists in the art to addressthe aforementioned deficiencies and inadequacies, which is to find a newTFT structure and a method for making the same with reduced leakagecurrent in the TFT and without additional TFT manufacturing and/orprocessing steps.

SUMMARY OF THE INVENTION

The present invention, in one aspect, relates to a method of forming athin film transistor (TFT) array panel. In one embodiment, the methodincludes the steps of: (i) forming a patterned first conductive layer,which includes a gate line and a shielding portion, on a substrate, (ii)forming a gate insulating layer on the patterned first conductive layerand the substrate, (iii) forming a patterned semiconductor layer on thegate insulating layer, (iv) forming a patterned second conductive layer,which includes a source electrode and a drain electrode, on thepatterned semiconductor layer, and a data line that is electricallyconnected to the source electrode, (v) forming a patterned passivationlayer on the patterned second conductive layer and the substrate, and(vi) forming a patterned transparent conductive layer on the passivationlayer. In one embodiment, the step of forming the patterned firstconductive layer further includes the step of forming a gap between thegate line and the shielding portion. The width of the gap is less than 6μm. In another embodiment, the step of forming the patterned firstconductive layer further includes forming a shielding line, disposedunder the data line.

In one embodiment, the step of forming the patterned first conductivelayer includes the steps of: (i) forming a first conductive layer on thesubstrate, (ii) forming a first photo-resist pattern on the firstconductive layer, (iii) etching the first conductive layer by using thefirst photo-resist pattern as a mask to form the gate line and theshielding portion adjacent to the gate line on the substrate, and (iv)removing the first photo-resist pattern.

In one embodiment, the step of forming the patterned semiconductor layerincludes the step of: (i) forming an intrinsic semiconductor layer onthe gate insulating layer, (ii) forming a doped semiconductor layer onthe intrinsic semiconductor layer, (iii) forming a second photo-resistpattern on the doped semiconductor layer, (iv) etching the intrinsicsemiconductor layer and the doped semiconductor layer by using thesecond photo-resist pattern as a mask to form the patternedsemiconductor layer on the gate insulating layer over the gate line andthe shielding portion, and (v) removing the second photo-resist pattern.

In one embodiment, the step of forming the patterned second conductivelayer includes the steps of: (i) forming a second conductive layer onthe doped semiconductor layer and the gate insulating layer, (ii)forming a third photo-resist pattern on the second conductive layer,(iii) etching the second conductive layer by using the thirdphoto-resist pattern as a mask to form the source electrode and thedrain electrode on the doped semiconductor layer, and the data line onthe gate insulating layer, and (iv) removing the third photo-resistpattern.

In one embodiment, the step of forming the patterned passivation layerincludes the steps of: (i) forming a passivation layer on the patternedsecond conductive layer and the substrate, (ii) forming a fourthphoto-resist pattern on the passivation layer, (iii) etching thepassivation layer by using the fourth photo-resist pattern as a mask toform a contact hole exposing a portion of the drain electrode, and (iv)removing the fourth photo-resist layer pattern.

In one embodiment, the step of forming the patterned transparentconductive layer includes the step of: (i) forming a transparentconductive layer on the patterned passivation layer, (ii) forming afifth photo-resist pattern on the transparent conductive layer, (iii)etching the transparent conductive layer by using the fifth photo-resistpattern as a mask to form the patterned transparent conductive layerelectrically connected to the drain electrode through the contact hole,and (iv) removing the fifth photo-resist pattern.

In one embodiment, the steps of forming the patterned semiconductorlayer, and forming the patterned second conductive layer are performedby using a half-tone mask or a gray-tone mask.

In one embodiment, the steps of forming the patterned semiconductorlayer, and forming the patterned second conductive layer include thesteps of: (i) forming an intrinsic semiconductor layer on the gateinsulating layer, (ii) forming a doped semiconductor layer on theintrinsic semiconductor layer, (iii) forming a second conductive layeron the doped semiconductor layer, (iv) forming a sixth photo-resistpattern by using the half-tone mask or the gray-tone mask, on the secondconductive layer, (v) etching the intrinsic semiconductor layer, thedoped semiconductor layer, and the second conductive layer by using thesixth photo-resist pattern as a mask to form the patterned semiconductorlayer, and the patterned second conductive layer on the patternedsemiconductor layer, and (vi) removing the sixth photo-resist pattern.

In one embodiment, the method further includes the step of forming astorage capacitor between the gate line and the patterned transparentconductive layer. The shielding portion is formed to have a width thatis at least equal to the width of the source electrode. In anotheraspect, the present invention includes a thin film transistor (TFT)array panel for a liquid crystal display device. In one embodiment, thethin film transistor (TFT) array panel has: (i) a substrate, (ii) apatterned first conductive layer having a gate line, a gate electrode,and a shielding portion that is adjacent to the gate line, all formed onthe substrate, (iii) a gate insulating layer formed on the firstpatterned conductive layer, (iv) a patterned semiconductor layer formedon the gate insulating layer over the gate electrode and the shieldingportion, (v) a second conductive layer having a source electrode and adrain electrode disposed on the patterned semiconductor layer, (vi) adata line electrically connected to the source electrode, (vii) apatterned passivation layer, formed on the source electrode, the drainelectrode and the data line, and exposing a portion of the drainelectrode, and (viii) a transparent conductive layer having a pixelelectrode formed on the patterned passivation layer and electricallyconnected to the drain electrode through a contact hole.

The shielding portion of the TFT array panel is substantiallyrectangular. The TFT array panel further includes a shielding line,disposed on the substrate and under the data line. The gate line, theshielding portion and the shielding line are formed as the same layer.The data line is disposed on the patterned semiconductor layer. In oneembodiment, the patterned semiconductor layer, the source electrode, thedrain electrode, and the data line are formed by using a half-tone maskor a gray-tone mask. The pixel electrode overlaps at least a portion ofthe gate line, thereby forming a storage capacitor. The gate electrodeand the shielding portion are separated with a gap, which is less than 6μm in width. The shielding portion is formed to have a width that is atleast equal to the width of the source electrode.

In one embodiment, the patterned semiconductor layer has an intrinsicsemiconductor layer that forms a doped semiconductor layer thereonafterimplanting. The drain electrode is an elongated conductive bar with afirst end, and an opposite, second end, and the source electrode is a“U” shaped conductive layer formed on the patterned semiconductor layer.The source electrode substantially surrounds the first end of the drainelectrode to form a “U” shaped channel area.

These and other aspects of the present invention will become apparentfrom the following description of the preferred embodiment taken inconjunction with the following drawings, although variations andmodifications therein may be affected without departing from the spiritand scope of the novel concepts of the disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings illustrate one or more embodiments of theinvention and, together with the written description, serve to explainthe principles of the invention. Wherever possible, the same referencenumbers are used throughout the drawings to refer to the same or likeelements of an embodiment, and wherein:

FIG. 1 shows a top view of a thin film transistor for a liquid crystaldisplay with reduced photo leakage current according to one embodimentof the present invention;

FIG. 2 shows a sectional view of a pixel structure for a liquid crystaldisplay with reduced photo leakage current along the A-A′ plane as shownin FIG. 1;

FIGS. 3A through 3E illustrate several steps of a manufacturing processof a thin film transistor array panel for a liquid crystal display withreduced photo leakage current according to one embodiment of the presentinvention;

FIGS. 4A through 4D illustrate several steps of a manufacturing processof a thin film transistor array panel for a liquid crystal display withreduced photo leakage current according to another embodiment of thepresent invention

FIGS. 5A through 5C show a top view, a sectional view and a moredetailed sectional view of a thin film transistor for a liquid crystaldisplay with a conventional “island out” TFT structure, respectively;

FIGS. 6A and 6B show a top view, a sectional view of a thin filmtransistor for a liquid crystal display with a conventional “island in”TFT structure, respectively; and

FIG. 7 displays a voltage vs. photo current curve and a voltage vs. darkcurrent curve comparing TFTs manufactured in accordance with oneembodiment of the present invention to the TFTs manufactured inaccordance with conventional “island out” and “island in” TFTstructures, where similar voltage is applied to the gates and sources ofthe corresponding thin film transistors to show a reduced photo leakagecurrent in the TFTs according to embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is more particularly described in the followingexamples that are intended as illustrative only since numerousmodifications and variations therein will be apparent to those skilledin the art. Various embodiments of the invention are now described indetail. Referring to the drawings, like numbers indicate like componentsthroughout the views. As used in the description herein and throughoutthe claims that follow, the meaning of “a”, “an”, and “the” includesplural reference unless the context clearly dictates otherwise. Also, asused in the description herein and throughout the claims that follow,the meaning of “in” includes “in” and “on” unless the context clearlydictates otherwise.

The description will be made as to the embodiments of the presentinvention in conjunction with the accompanying drawings in FIGS. 1-7. Inaccordance with the purposes of this invention, as embodied and broadlydescribed herein, this invention relates to a method to reduce photoleakage current of a thin film transistor for a liquid crystal display.

A top view of a thin film transistor (TFT) 100 for a liquid crystaldisplay (LCD) with reduced photo leakage current is shown in FIG. 1according to one embodiment of the present invention. FIG. 2 shows asectional view of the TFT 100 along the A-A′ plane shown in FIG. 1.

A plurality of TFTs 100 can be utilized to form a TFT array panel for anLiquid Crystal Display (LCD) device. The TFT array panel for a liquidcrystal display device is formed with a plurality of pixel structurewith thin film transistors arranged in a matrix form to support aplurality of LCD pixel display areas arranged correspondingly, and toform a larger display area having the plurality of LCD pixel displayareas.

For each TFT of the TFT array panel, it has a substrate 5, and apatterned first conductive layer 10 having a gate line 11, a gateelectrode 106, and a shielding portion 30, adjacent to the gate line 11,all formed on the substrate 5. In one embodiment, the shielding portion30 is electrically floated. Each TFT also has a gate insulating layer 12formed on the patterned first conductive layer 10, a patternedsemiconductor layer 14 formed on the gate insulating layer 12 over thegate electrode 106 and the shielding portion 30, a patterned secondconductive layer 18 having a source electrode 102 and a drain electrode104 disposed on the patterned semiconductor layer 14, and a data line 13(shown in FIG. 4B) electrically connected to the source electrode 102.The shielding portion 30 is not overlapped with the data line 13. Apatterned passivation layer 20 is formed on the source electrode 102,the drain electrode 104 and the data line 13 such that a portion of thedrain electrode 104 is exposed. A patterned transparent conductive layer22 having a pixel electrode 32 is formed on the patterned passivationlayer 20 and electrically connected to the drain electrode 104 through acontact hole 110, which is defined by the patterned passivation layer20.

The shielding portion 30 formed on the TFT substrate is substantiallyrectangular when viewed from the top as shown in FIG. 1. The gate line11 and the shielding portion 30 are formed as parts of the patternedfirst conductive layer 10.

In one embodiment, the patterned first conductive layer 10 having thegate line 11, the gate electrode 106, and the shielding portion 30 isformed on the substrate 5. The patterned semiconductor layer 14 havingthe intrinsic semiconductor layer 15 and the doped semiconductor layer16 is formed on the gate insulating layer 12 over the gate electrode 106and the shielding portion 30. The data line 13 is disposed on the gateinsulating layer 12.

In another embodiment, the patterned first conductive layer 10 havingthe gate line 11, the gate electrode 106, the shielding portion 30, anda shielding line 35 is formed on the substrate 5, as shown in FIG. 4A.As shown in FIG. 4B, the patterned semiconductor layer 14 has anintrinsic semiconductor layer 15 and a doped semiconductor layer 16. Thedoped semiconductor layer 16 may be formed after the intrinsicsemiconductor layer 15 is implanted. The data line 13 is disposed on thepatterned semiconductor layer 14. The shielding line 35 is under thedate line 13. The patterned semiconductor layer 14, and the data line 13are formed by using a half-tone mask or a gray-tone mask.

The pixel electrode 32, as shown in FIG. 3E, is formed as part of thepatterned transparent conductive layer 22, which overlaps at least aportion of the gate line 11 to define a space therebetween, which isoccupied by the gate insulating layer 12, thereby forming a storagecapacitor. The gate electrode 106 and the shielding portion 30 areseparated with a gap 140, which is less than 6 μm in width. Theshielding portion 30 is formed to have a width that is at least equal tothe width W of the source electrode 102 as shown in FIG. 1.

Referring now to FIG. 1, the drain electrode 104 is formed as anelongated conductive bar with a first end 104a, and an opposite, secondend 104b, and the source electrode 102 is formed as a “U” shapedconductive layer that is formed on the patterned semiconductor layer 14.The source electrode 102 substantially surrounds the first end 104a ofthe drain electrode 104 to form a corresponding “U” shaped channel area112. The transparent conductive layer 22 can be made of an Indium TinOxide (ITO) layer, an Indium Zinc Oxide (IZO) layer, or a combination ofthese materials.

A portion of the drain electrode 104 overlaps at least a portion of thepatterned transparent conductive layer 22, as shown in FIG. 2. In theoverlapped area, a contact through hole 110 is formed to allow apatterned second conductive layer 18, of which the drain electrode 104is a part, to electrically coupled to the patterned transparentconductive layer 22. The patterned transparent conductive layer 22 formsa pixel display area. The pixel display area overlaps at least a portionof the patterned first conductive layer 10.

The present invention in another aspect relates to a method ofmanufacturing thin film transistor (TFT) array panel with reduced photoleakage current for a liquid crystal display panel. In one embodiment,the method of manufacturing thin film transistor (TFT) array panel withreduced photo leakage current for a liquid crystal display panelincludes the steps of:

-   -   (i) forming a patterned first conductive layer 10, which        includes a gate line 11, a gate electrode 106, and a shielding        portion 30, on a substrate 5, where the shielding portion 30 is        electrically floated;    -   (ii) forming a gate insulating layer 12 on the patterned first        conductive layer 10 and the substrate 5;    -   (iii) forming a patterned semiconductor layer 14 on the gate        insulating layer 12;    -   (iv) forming a patterned second conductive layer 18, which        includes a source electrode 102 and a drain electrode 104, on        the patterned semiconductor layer 14, and a data line 13 that is        electrically coupled to the source electrode 102, where the        shielding portion 30 is not overlapped with the data line 13.    -   (v) forming a patterned passivation layer 20 on the patterned        second conductive layer 18 and the substrate 5; and    -   (vi) forming a patterned transparent conductive layer 22 on the        passivation layer 20.

These steps can be performed in the order as set forth above in oneembodiment of the present invention. Alternatively, they may beperformed in other orders as known to people skilled in the art.

FIGS. 3A through 3E illustrate several steps of a manufacturing processof a thin film transistor for a liquid crystal display with reducedphoto leakage current according to one embodiment of the presentinvention. It is noted that although the process for manufacturing onlyone TFT is described here in the specification, one or more TFTs can bemade in similar processes.

A first photo-resist pattern is used to form a patterned firstconductive layer 10, which includes a gate line 11, a gate electrode106, and a shielding portion 30 as shown in FIG. 3A. In operation, thefirst photo-resist pattern is positioned to overlap at least a portionof a pixel electrode (not shown in FIG. 3A). With the first photo-resistpattern, the gate line 11, the gate electrode 106, and the shieldingportion 30 are formed by:

-   -   (i) depositing a first conductive layer on the substrate 5 using        a Physical Vapor Deposition (PVD) process;    -   (ii) depositing a first photo-resist pattern on the first        conductive layer;    -   (iii) etching the first conductive layer by using the first        photo-resist pattern as a mask to form a gate line 11, a gate        electrode 106, and a shielding portion 30 on the substrate 5,        respectively; and    -   (iv) removing the first photo-resist pattern on the gate line        11, the gate electrode 106, and the shielding portion 30.

Again, these steps can be performed in the order as set forth above, orin one or more alternative orders.

The etching process can be a dry etching process, a wet etching process,or a combination of both. The first conductive layer can be made ofmetal, metal oxide, or a combination of both. A gap 140 is formedbetween the gate electrode 106 and the shielding portion 30. The widthof the shielding portion 30 formed to be at least equal to the width ofthe “U” shaped source electrode 102, as shown in FIG. 1.

FIG. 3B partially shows the steps for forming a patterned semiconductorlayer 14 as shown in FIG. 2) by using a second photo-resist pattern:

-   -   (i) forming a gate insulating layer 12 layer on the gate line        11, the gate electrode 106 and the shielding portion 30 using a        first Plasma Enhanced Chemical Vapor Deposition (PECVD) process;    -   (ii) depositing a layer of intrinsic semiconductor on (such as        layer 15 shown in FIG. 2) the gate insulating layer 12 using a        second PECVD process;    -   (iii) depositing a layer of doped semiconductor layer 16 on the        layer of intrinsic semiconductor using a third PECVD process;    -   (iv) depositing a second photo-resist pattern on the doped        semiconductor layer 16;    -   (v) dry etching the doped semiconductor layer 16 and the        intrinsic semiconductor layer by using the second photo-resist        pattern as a mask to form the patterned semiconductor layer 14;        and    -   (vi) removing the second photo-resist pattern on the doped        semiconductor layer 16.

Similarly, these steps can be performed in the order as set forth above,or in one or more alternative orders.

A third photo-resist pattern is used to form a patterned secondconductive layer 18, which includes a data line 13, the source electrode102, and the drain electrode 104, as shown in FIG. 3C. With the thirdphoto-resist pattern, the data line 13, the source electrode 102, andthe drain electrode 104 are formed according to several steps asfollows:

-   -   (i) depositing a second conductive layer on the doped        semiconductor layer 16 and the gate insulating layer 12 using a        PVD process;    -   (ii) depositing a third photo-resist pattern on the second        conductive layer;    -   (iii) etching the second conductive layer by using the third        photo-resist pattern as a mask to form the data line 13, the        source electrode 102 and the drain electrode 104; and    -   (iv) removing the third photo-resist pattern on the data line        13, the source electrode 102 and the drain electrode 104.

Likewise, these steps can be performed in the order as set forth above,or in one or more alternative orders.

The etching process can be a dry etching process, a wet etching process,or a combination of both. The second conductive layer can be made ofmetal, metal oxide, or a combination of both.

A fourth photo-resist pattern is used to form a patterned passivationlayer 20, as shown in FIG. 3D, according to several steps as follows:

-   -   (i) depositing a passivation layer on the data line 13, the        source electrode 102 and the drain electrode 104 using a PECVD        process;    -   (ii) depositing a fourth photo-resist pattern on the passivation        layer;    -   (iii) etching the passivation layer by using the fourth        photo-resist pattern as a mask to form a contact through hole        110 (as shown in FIG. 2) as the contact between the transparent        conductive layer 22 and the drain electrode 104; and    -   (iv) removing the fourth photo-resist pattern.

Also, these steps can be performed in the order as set forth above, orin one or more alternative orders.

The etching process can be a dry etching process, a wet etching process,or a combination of both.

A fifth photo-resist pattern is used to form a patterned transparentconductive layer 22 having a pixel electrode 32, as shown in FIG. 3E,according to several steps as follows:

-   -   (i) depositing a transparent conductive layer on the patterned        passivation layer 20 by using a PVD process;    -   (ii) depositing a fifth photo-resist pattern on the transparent        conductive layer;    -   (iii) etching the transparent conductive layer by using the        fifth photo-resist pattern as a mask to form the pixel electrode        32; and    -   (iv) removing the fifth photo-resist pattern on the pixel        electrode 32.

The etching process can be a dry etching process, a wet etching process,or a combination of both. In one embodiment, the transparent conductivelayer is an indium tin oxide (ITO) layer. In another embodiment, thetransparent conductive layer is an indium zinc oxide (IZO) layer. In yetanother embodiment, the transparent conductive layer 22 can be formedwith a combination of both ITO and IZO.

FIGS. 4A through 4D illustrate several steps of a manufacturing processof a thin film transistor for a liquid crystal display with reducedphoto leakage current according to another embodiment of the presentinvention. It is noted that although the process for manufacturing onlyone TFT is described here in the specification, one or more TFTs can bemade in similar processes.

As shown in FIG. 4A, a first shielding pattern is used to form apatterned first conductive layer 10, which includes a gate line 11, agate electrode 106, a shielding portion 30, and a shielding line 35. Thesteps can be performed as set forth above.

As shown in FIG. 4B, after the gate insulating layer 12 is formed on thefirst patterned conductive layer 10, the patterned semiconductor layer14 and the patterned second conductive layer 18 are performed by using ahalf-tone mask or a gray-tone mask.

The patterned semiconductor layer 14 and the patterned second conductivelayer 18 are formed according to several steps as follows:

-   -   (i) depositing a layer of intrinsic semiconductor 15 on the gate        insulating layer 12;    -   (ii) depositing a layer of doped semiconductor layer 16 on the        layer of intrinsic semiconductor 15;    -   (iii) depositing a second conductive layer on the layer of doped        semiconductor layer 16;    -   (iv) forming a sixth photo-resist pattern by using the half-tone        mask or the gray-tone mask, on the second conductive layer;    -   (v) etching the layer of intrinsic semiconductor 15, the layer        of doped semiconductor layer 16, and the second conductive layer        by using the sixth photo-resist pattern as a mask to form the        patterned semiconductor layer 14 and the data line 13, the        source electrode 102 and the drain electrode 104 on the        patterned semiconductor layer; and    -   (vi) removing the sixth photo-resist pattern.

The shielding line 35 is disposed under the data line 13.

Next, a patterned passivation layer 20 and a patterned transparentconductive layer 22 having a pixel electrode 32 are formed, as shown inFIG. 4C and FIG. 4D. The steps can be performed as set forth above.

The TFT structure provided by the present invention represents a noveland significant technology advance over the current available TFTstructures. FIG. 7 displays a voltage vs. photo current curve and avoltage vs. dark current curve comparing TFTs manufactured in accordancewith one embodiment of the present invention to the TFTs manufactured inaccordance with conventional “island out” and “island in” TFTstructures, where similar voltage is applied to the gates and sources ofthe corresponding thin film transistors to show reduced photo leakagecurrent the TFTs according to one embodiment of the present invention.

The dark current is a current passing through the drain electrode andthe source electrode when there is not sufficient environmentallighting. The photo current is a current passing through the drainelectrode and the source electrode when there is normal or strongenvironmental lighting. The voltage between the drain electrode and thesource electrode is set to be at VDS=10V, in this example.

The curve 602 represents the dark current of a conventional TFT with an“island-in” structure. The curve 612 represents the dark current of aconventional TFT with an “island-out” structure. The curve 622represents the dark current of a TFT according to one embodiment of thepresent invention. The curve 604 represents the photo current of the TFTwith an “island-in” structure. The curve 614 represents the photocurrent of the

TFT with an “island-out” structure. The curve 624 represents the photocurrent of the TFT according to one embodiment of the present invention.From FIG. 7, the dark current (curve 622) of the TFT of the presentinvention is slightly larger than the other two TFT structures, but itis still significantly smaller than any of photo currents 604, 614, and624. However, the photo current 624 of the TFT according the presentinvention is significantly smaller than the photo current 614 of the“island-out” structure TFT, and almost identical to the photo current604 of the “island-in” structure TFT. The comparisons of the photocurrents among these three TFT types indicate that the presentinvention, among other things, provides a method to achieve the goal ofreducing the photo-leakage-current with a simplified manufacturingprocess.

The foregoing description of the exemplary embodiments of the inventionhas been presented only for the purposes of illustration and descriptionand is not intended to be exhaustive or to limit the invention to theprecise forms disclosed. Many modifications and variations are possiblein light of the above teaching.

The embodiments were chosen and described in order to explain theprinciples of the invention and their practical application so as toenable others skilled in the art to utilize the invention and variousembodiments and with various modifications as are suited to theparticular use contemplated. Alternative embodiments will becomeapparent to those skilled in the art to which the present inventionpertains without departing from its spirit and scope. Accordingly, thescope of the present invention is defined by the appended claims ratherthan the foregoing description and the exemplary embodiments describedtherein.

1. A thin film transistor (TFT) array panel for a liquid crystal displaydevice, comprising: (i) a substrate; (ii) a patterned first conductivelayer having a gate line, a gate electrode, and a shielding portion thatis adjacent to the gate line, all formed on the substrate, the shieldingportion being electrically floated; (iii) a gate insulating layer formedon the first patterned conductive layer; (iv) a patterned semiconductorlayer formed on the gate insulating layer, having a portion thatoverlaps the shielding portion; (v) a patterned second conductive layerhaving a source electrode and a drain electrode disposed on thepatterned semiconductor layer, and a data line electrically connected tothe source electrode; (vi) a patterned passivation layer, formed on thesource electrode, the drain electrode and the data line, and exposing aportion of the drain electrode; and (vii) a transparent conductive layerhaving a pixel electrode formed on the patterned passivation layer andelectrically connected to the drain electrode through a contact hole. 2.The TFT array panel of claim 1, wherein the shielding portion issubstantially rectangular.
 3. The TFT array panel of claim 1, whereinthe gate line, the shielding portion are formed as the same layer. 4.The TFT array panel of claim 1, wherein the data line is disposed on thepatterned semiconductor layer.
 5. The TFT array panel of claim 1,wherein the pixel electrode overlaps at least a portion of the gateline, thereby forming a storage capacitor.
 6. The TFT array panel ofclaim 1, wherein the gate electrode and the shielding portion areseparated with a gap.
 7. The TFT array panel of claim 6, wherein thewidth of the gap is less than 6 μm.
 8. The TFT array substrate panel ofclaim 1, further comprising a shielding line, disposed on the substrateand under the date line.
 9. The TFT array panel of claim 1, wherein theshielding portion is formed to have a width that is at least equal tothe width of the source electrode.
 10. The TFT array panel of claim 1,wherein the patterned semiconductor layer comprises an intrinsicsemiconductor layer and a doped semiconductor layer.
 11. The TFT arraypanel of claim 1, wherein the drain electrode is an elongated conductivebar with a first end, and an opposite, second end, and the sourceelectrode is a “U” shaped conductive layer formed on the patternedsemiconductor layer, and wherein the source electrode substantiallysurrounds the first end of the drain electrode to form a “U” shapedchannel area.
 12. The TFT array panel of claim 1, wherein the shieldingportion is not overlapped with the data line.